1. Field of the Invention
The invention relates to a static type semiconductor memory device and a data processing device, and more particularly to improved peripheral circuits in a static-RAM (SRAM) with memory cells or flip-flop circuits.
2. Related Art Description
A typical high resistance type static-RAM (SRAM) which employs an internal synchronous mechanism is constituted as shown in FIG. 21. The SRAM has memory cell arrays (Blocks 0 to 15) formed, as shown in FIG. 21, by arranging a plurality of polysilicon memory cells of the high resistance type 1 in a matrix, and a peripheral circuit which performs writing and reading operations wherein one or more memory cells are selected and data or information is written into or read from the selected cells.
The peripheral circuit shown in FIGS. 21 and 22 is generally constituted by a chip control circuit 21 which supplies a chip selecting signal CS, write enable signal. WE and output enable signal OE to prescribed circuits on a chip on the basis of control signals provided from the outside, an X-decoder and word line buffer circuit 22 for selecting word lines, a Y-decoder 24 for selecting transfer gate circuits 23, a Z-address buffer circuit (block signal generator) 25 which generates a block signal BLOCK for selecting one or more of Blocks 0 to 15, an X-address buffer circuit 26 for sending information to the X-decoder 22, a Y-address buffer circuit 27 for sending information to the Y-decoder 24, address-transition detecting circuits (ATDs) 28, 29 and 30 which detect transition of the address input signals of the X, Y and Z-address buffer circuits and generate pulses, an internal synchronizing, or timing, circuit 31 for generating synchronizing, or timing, signals in order to precharge and equalize bit lines BL, BL just before reading out in a manner to utilize basic pulses generated from the ATDs, a data line loading circuit 32 which controls the potentials on the data lines when writing and reading, a sense amplifier circuit 33 for producing amplified outputs SO, SO and for detecting small voltages SIN, SIN which emerge on the data line through the transfer gate circuit 23 from memory cells when reading, a writing driver circuit 34 which sends data for writing to the bit lines BL, BL when writing, a bit line loading circuit 35 which controls loading of the bit lines BL, BL when writing and reading and for equalizing the bit lines BL, BL so as to have the same potential just before reading, a bit/data line loading control circuit 36 for controlling the bit line loading circuit 35 and data line loading circuit 32, an I/O buffer circuit 37, and a sense amplifier control circuit 38 for generating a sense amplifier control pulse .phi.sa which drives the sense amplifier circuit 33 dynamically according to a signal supplied from the internal synchronizing circuit. 31.
The X-decoder and word line buffer circuit 22 is conventionally constituted as shown in FIG. 23, wherein it comprises a NAND gate having three inputs for receiving buffer outputs R1-R3 or R1-R3 from the X-address buffer circuit 26, and a NOR gate having two inputs for receiving an output of the NAND gate and a buffer output Ro or Ro from the X-address buffer circuit 26. In circuit 22 a selected word line WL (WL1, WL2 or the like) is set to supply a potential Vdd of high level (hereinafter referred to as "H"). To the word lines WL are connected memory cells 1 as shown in FIG. 24. In the memory cells 1 connected to a selected word line WL, data writing or reading is carried out via the bit lines BL, BL.
The potential of the selected word line WL is set to be the supplied potential Vdd of high level "H", that is of logically high level, by means of logic circuits forming the X-decoder and word line buffer circuit 22. The following description will be based on a system in which data writing is carried out by setting the bit line BL to be "H" and setting the bit line BL to be low level potential, or ground potential (hereinafter referred to as "L").
The potentials at the memory nodes n1, n2 in the memory cell 1 are established as follows. Since the potential of the word line Vw1 is set to be the supplied potential Vdd, the maximum potential of the memory node n1 is defined by the following expression. EQU V1=Vw1-Vt1-Vb=Vdd-Vt1-Vb (1)
Wherein Vdd is a supplied potential, Vt1 is the threshold voltage of n-channel MOS transistors N3, N4 as transfer gates, and Vb is a voltage drop component resulting from backgate effect. The memory nodes n1, n2 in the memory cell 1 are connected to the supplied potential Vdd through the polysilicon high resistances HR1, HR2, respectively. The values of these polysilicon high resistances HR1, HR2 are generally set to be in the range of several hundred giga-ohms to a few tera-ohms in order to limit current flow to the nodes during the waiting period (stationary period). The currents through the resistances HR1, HR2 are very small, so that the maximum potential of the memory node n1 during writing operation, which is obtained from the expression (1), is not likely to rise as high as the supplied potential Vdd. If the polysilicon high resistances HR1, HR2 are set to have smaller resistance values in order to obtain the pull-up effect, the current consumption increases during non-operating conditions. The condition of EQU V1&gt;Vt2 (2)
must be satisfied to hold data in the flip-flop of the memory cell 1, wherein the maximum potential V1 is given by the expression (1), and Vt2 is a threshold voltage of the n-channel MOS transistors N1, N2. Thus, when writing data, it is necessary to satisfy the following condition obtained by substituting expression (1) into expression (2): EQU Vw1-Vt1-Vb=Vdd-Vt1-Vb&gt;Vt2 (3)
If a writing operation is carried out under conditions such that expression (3) is not satisfied, both of the n-channel MOS transistors N1 and N2 in the flip-flop assume their off-state and therefore will not be able to hold data in the memory cell 1. In this non-operating state wherein the memory cell 1 does not function as a flip-flop, when noise enters memory cell 1 or a reading operation begins erroneously, the data in the memory cell 1 are easily destroyed.
While, according to semiconductor technology, it is necessary to satisfy Vdd&gt;2.4 v on the assumption that Vt1=Vt2=0.9 v, Vb=0.6 V. This means that the SRAM of the prior art cannot be written to or read properly unless the supplied voltage Vdd is higher than 2.4 v.
Table calculators commonly require an electric battery as a power source, with a source voltage of 3v, for example. However, the voltage value of the battery drops during its lifetime. When the SRAM of the prior art is powered, in such a calculator, by the 3 volt battery, the frequency of the battery change will increase because the SRAM will not work after the voltage drop becomes more than 0.6 v.
On the other hand, there is known a fully CMOS type memory cell in which p-channel MOS transistors are used instead of polysilicon high resistances HR1, HR2, and an SRAM constituted by the fully CMOS type memory cells is driven by a low supply voltage. However, this type of memory cell tends to have a larger size because it must be provided with an isolation region for device isolation between an n-channel MOS transistor and a p-channel MOS transistor, as known in semiconductor technology. In contrast, memory cells of high resistance type have the benefit of smaller cell size since it is possible to form a three-dimensional structure with polysilicon high resistance on an insulation film covering the n-channel MOS transistor. However, an SRAM equipped with memory cells of the high resistance type has the drawback that it cannot be operated with a low voltage power supply as mentioned above.
Consequently, two methods are proposed in order to satisfy expression (3), above, in use of a low voltage power supply in such a manner that memory cells of the high resistance type can be operated properly.
One of these methods is to lower the threshold voltages Vt1, Vt2, and the other is to decrease the voltage drop Vb caused by the backgate effect. To decrease the threshold voltages Vt1, Vt2 complicates the process conditions and causes deterioration of memory cell stability due to changing the threshold voltage of n-channel MOS transistors N1, N2, N3, and N4. Hence this method is not practical. To decrease the value of the voltage Vb during writing operations is not practical, either. Because the substrate capacitance of the memory cell is large, this method induces increases in electricity consumption by added control circuits.